Field of the Invention
The present invention relates to an electrically erasable and programmable non-volatile semiconductor storage device.
Description of the Related Art
NAND-type flash memory has a cell array that includes a plurality of NAND cell units arranged therein, each of which has a plurality of memory cells connected in series. Each end of a NAND cell unit is connected to a bit line and a source line via selection gate transistors, respectively.
The control gates of memory cells in each NAND cell unit are connected to different word lines. In NAND-type flash memory, a plurality of memory cells are connected in series, sharing a source and a drain with each other. In addition, these memory cells share components, such as selection gate transistors or associated bit-line or source-line contacts. This may reduce the size of a unit memory cell. Furthermore, device regions including word lines and memory cells are generally arranged in a simple stripe pattern, which is suitable for shrinking and thus provides large capacity flash memory.
In addition, data program and erase are performed in NAND-type flash memory by causing FN tunnel current to flow through many cells at the same time. Specifically, data program is performed in pages, where a set of memory cells sharing one word line represent one or two pages. Data erasing is performed in blocks, where a block is defined as a set of NAND cell units sharing a word line and a selection gate line.
In addition, when data erase is performed in blocks in the NAND-type flash memory, verify read (erase verify) is performed to verify whether an erase state within a certain range of a threshold voltage is achieved (see, for example, Japanese Patent Laid-Open No. 2000-236031). As a result of the erase verify operation, if it is determined that the data erase is not sufficient, then additional erase and erase verify operations are iterated in a similar manner, increasing the erase voltage in stages (step up).
On the other hand, iterations of data program and erase on one memory cell can lead to progressive degradation of the tunnel insulation film of the memory cell, which may reduce the reliability of memory. Therefore, the stress on memory cells due to program and erase voltages should be reduced as much as possible. Reducing such stress on memory cells improves the reliability of memory and contributes to a longer lifetime of the memory cells.